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Cypress Semiconductor /psoc63 /SCB0 /I2C_STATUS

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Interpret as I2C_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BUS_BUSY)BUS_BUSY 0 (I2C_EC_BUSY)I2C_EC_BUSY 0 (S_READ)S_READ 0 (M_READ)M_READ 0CURR_EZ_ADDR0BASE_EZ_ADDR

Description

I2C status

Fields

BUS_BUSY

I2C bus is busy. The bus is considered busy (‘1’), from the time a START is detected or from the time the SCL line is ‘0’. The bus is considered idle (‘0’), from the time a STOP is detected. If SCB block is disabled, BUS_BUSY is ‘0’. After enabling the block, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period).

For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions).

For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions).
I2C_EC_BUSY

N/A
S_READ

N/A
M_READ

N/A
CURR_EZ_ADDR

N/A
BASE_EZ_ADDR

N/A

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data